Nanotechnology in VLSI Design and Nanoelectronics
By Aditya Mittal
Background:
Theoretical Basis
Most computer scientists and
engineers today are aware of the shrinking transistor sizes, for it has been a
continuous process since the advent of vacuum tubes, and the cause of rapid
development of computing technologies.
Today, we use CMOS (Complementary Metal Oxide Semiconductor) technology
to build our transistors. The advantages
of CMOS technology over other technologies is that they have no static power
dissipation, logic levels are fully restored, integration levels are high, and
rise and fall transition times are of the same order. In the past, we have been using micron
technology. In 2001, we began using
.25μm CMOS technology which is said to be deep sub-micron (DSM) technology. Other DSM technologies include the
.180μm and the .130μm technologies. Next we have nanotechnologies at transistor
sizes of 90nm (.090μm), 65nm (.065μm), and 45nm (.045μm).
However, as physicists and engineers take diverging
roads it has been argued that “microelectronics, even if the gate size of the
transistor is 50 nm, is not an implementation of nanoelectronics, as no new
qualitative physical property related to reduction in size are being
exploited.” The road that the engineers
are taking is still being called microelectronics even though it might deal
with nanoscale transistors. To avoid
confusion, we shall refer to nanoscale transistors as nanotechnology, but not
as nanoelectronics. For the next ten to
fifteen years we shall continue to see applications of nanotechnology but
nanoelectronics can be expected to remain a research field as we bridge the gap
and truly begin using nanoelectronics in everyday technological applications.
Current nanoelectronics have shown the development of
electronic components at the molecular level.
However, it remains unclear to most how these nanoelectronic components
can be incorporated into larger macroscopic structures to create usable and
practical electronic circuits. Some
believe that there will be a gradual switch from CMOS technology to molecular
electronics technology as we learn more and begin incorporating small molecular
components within the existing chip technology.
Others believe that a dramatic switch will occur as a next generation
“Intel” based on molecular nanoelectronics emerges.
Indeed, VLSI (Very Large Scale Integration) design
engineers are beginning to face new problems as the integrated chips increase
in density. For example, the electrons
are jumping the gap between metal layers.
One common solution is to introduce new types of metallic materials into
the chip. However, this is not a
sufficient and viable solution in the long term. Actual nanostructures, such as current
carrying carbon nanotubes for wires, need to be introduced into the chip to
handle the various problematic cases.
After more than three decades of research and experience in chip making,
VLSI design engineers had developed certain DRC (Design Rule Checking) methods
to confirm that a circuit will work with a certain technology. Software tools such as those of Cadence and
Synopsis helped designers quickly establish the stability and correctness of a
circuit design. However, with
nanotechnology this method of checking a circuit is no longer enough due to
quantum effects such as tunneling from one metal layer to another. Therefore, research in applying statistical
mechanics to deal with probabilistic behavior of metal to metal jumping
electron in the chip is also occurring.
This too may lead to the nanoscale electronics of the near future. Let us introduce the term “nanoVLSI” to
discuss this phenomenon as “nanoelectronics” has already been taken. This will allow us to maintain broader scope
and also consider the interactions and systems between many nanoscale
transistors.
The advantage of the engineering approach over that of
the physicists is that a lot is already established and the costs of
improvement are many magnitudes smaller.
However, unlike the approach of the physicists, this approach may soon
result in a deadlock, forcing us to discard current chip making
nanotechnologies and moving on into the realm of nanoelectronics. Some intermediate paths may be viable for the
next decade. Therefore, in order to get
a true vision of the nanoelectronics of the future, we must consider the
advances in both experimental and theoretical physics as well as electronics
engineering.
Integration of nanostructures and CMOS technology:
The Big Problem with Nanodevices
Large scale integration of nanostructures at room
temperature smaller than 10nm is far too sensitive to size variations of even a
few atomic widths to be useful.
One likely solution within next 20 years
An
advanced CMOS sub-system incorporating fault-tolerant versions of memory
matrices and number crunching processors and a layer of ultra dense molecular
electron devices would come together to form hybrid integrated circuits, termed
“CMOL.” CMOL devices would be fabricated
by chemically-assisted self-assembly from solution on few-nm-pitch nanowire
arrays connecting them to the CMOS stack.
See Dmitri B Strukov’s paper titled “CMOL
FPGA: a reconfigurable architecture for hybrid digital circuits with
two-terminal nanodevices.” Active
devices in CMOL circuits may be kept at densities as high as 1012 cm2
and provide up to 1020 operations per second, at manageable power
consumption.
See “Afterlife for Silicon: CMOL
Circuit Architectures” at http://pavel.physics.sunysb.edu/~likharev/nano/IEEENANO05.pdf
for more detail on CMOL memories, CMOL FPGA: Boolean Logic Circuits, and CMOL
CrossNets: Neuromorphic Networks.
CrossNets may be able to provide advanced image recognition and advanced
intelligent information processing.
Architecture:
While much research in
nanoelectronics is occurring, very few companies have focused on architecture
and how all these new technologies such as nanoelectronics and photonics will
be incorporated with current technology in order to proceed. The two leading companies are HP and
IBM. HP has a number of patents in this
direction, including an architecture known as the “crossbar architecture.” Crossbar architecture is a fully connected
array of N horizontal input wires and N vertical output wires that can be
connected by closing the switches known as cross points.
Figure 1: Crossbar Architecture
http://www.cs.sfu.ca/~ljilja/cnl/presentations/maryam/maryam_thesis/sld007.htm
HP has developed crossbars with wires made of
nanotubes that simulate standard computer circuits. Despite the high rate of defects in nanowire
crossbar arrays, the simulations show that such architectures can be used to
make computer processors by building in redundancy, similar to redundancy in
DNA computing, and despite the need for a high degree of redundancy, nanowire
crossbar arrays can contain as many as 100 times more devices in a given area
than today's chip technologies. (http://www.trnmag.com/Stories/2004/090804/Chip_architecture_uses_nanowires_090804.html)
With Crossbar Architecture HP researchers have built
components including logic, buffer and routing tiles. “Logic tiles can be configured into simple
arrangements of logic gates that carry out basic computation. Buffer tiles
provide the electrically required separation between logic tiles. Routing tiles
control the flow of signals between groups of logic tiles.” http://www.trnmag.com/Stories/2004/090804/Chip_architecture_uses_nanowires_090804.html
HP's Teramac project
It was mentioned above that crossbar arrays can
contain as many as 100 times more devices in a given area than today’s chip
technologies. This idea has been
demonstrated with HP’s Teramac project.
See “A Defect-Tolerant Computer
Architecture: Opportunities for Nanotechnology” by James
R. Heath, Philip J. Kuekes, Gregory S. Snider, R. Stanley Williams
at http://www.sciencemag.org/cgi/reprint/280/5370/1716.pdf. The Teramac is a customizable computer system
that when fully upgraded supports half a gigabyte of RAM and provides hardware support
for large multiported register files. It
is built from packaging custom FPGA’s to provide millions of gates on which a
custom circuit can be compiled in about an hour. It has been estimated that even if up to 50%
of the wires running inside the Teramac might be defective, it can still
operate successfully. This is important
in consideration of system defects, redundancy and probabilities as we shall
soon look into. Using this system one
can study emerging systems that have millions of gates such as DNA systems (for
example DNA string matching algorithms have been studied) or one might also
study the nano-crosswire arrays discussed above. Defect tolerance and artery extraction
filtering of 3D MRI data are just some of the things being studied with the
Teramac’s great capability.
Silicon Nanophotonics
Futuristic silicon chip with
monolithically integrated photonic and electronic circuits
This hypothetic chip performs
all-optical routing of mutliple N optical channels each supporting 10Gbps data
stream. N channels are first demultiplexed in WDM photonic circuit, then
rearranged and switched in optical cross-connect OXC module, and multiplexed
back into another fiber with new headers in WDM multiplexer. Data packets are
buffered in optical delay line if necessary. Channels are monitored with
integrated Ge photodetector PD. CMOS logical circuits (VLSI) monitor the
performance. Electrical pads are connecting the optoelectronic chip to other
chips on a board via electrical signals.
(http://domino.research.ibm.com/comm/research_projects.nsf/pages/photonics.index.html)
The project depicted above is one IBM is actively
pursuing along with many other companies and institutions. It is generically referred to as a photonic
system-on-chip. Refer to the section
titled “Photonics and Electronics” in my description of Nanotechnology. This description is available at http://scientificchess.com/articles/Nanotechnology.htm.
Silicon Nanoelectronics
Shown above is an image taken from
Hybrid Carbon and Silicon
Nanoelectronics
A
carbon Nanotube FET based inverter (source: IBM)
The goal of Carbon Nanoelectronics is to create
integrated electronic systems using molecules such as pentacene and carbon
nanotubes as the active electronic elements to obtain new functionality. Furthermore, for improved architectures
Carbon and Silicon Nanoelectronics can be combined to form hybrid chips that
may provide greater and more optimized functionality. See for example http://www.cns.cornell.edu/C-nanoelectronics05McEuen.html. This is an extremely underdeveloped area
presently.
IBM's self healing Blue Gene project
The blue gene project aims to explore the frontiers of
supercomputing. At a peak speed of 360
Teraflops, it became the fastest supercomputer in the world in November
2004. It is used to develop an improved
understanding of computer architecture, software required to program and
control massively parallel systems, and important biological processes such as
protein folding. Like the Teramac,
described above, the Blue Gene is an indispensable tool to developing an
understanding of these large scale systems of the future. The blue gene is primarily being used to
study molecular dynamics which is a key step to the development of
nanoelectronics. For more information http://domino.research.ibm.com/comm/research.nsf/pages/r.arch.html
is IBM’s computer architecture research webpage where many other projects along
with the Blue Gene are listed.
Ideas, Experiments and Research in Nanoelectronics:
Electron transport in nanostructures such as Quantum
Dots
Electron transport is the fundamental idea behind
developing transistor like electronic devices.
In order to build a transistor one needs a “source, drain, and a
gate.” The gate controls the flow of electrons from the source to the
drain. If we were to build a transistor
with photons we could have a mechanical gate that blocked the photons. With electronic transistors we normally have
a voltage based gate. The voltage that
is applied to the gate is known as gate voltage and its amplitude determines
whether or not current flows from source to drain. This voltage is known as the “gate voltage.”
With nanoelectronics, we build transistors out of
nanostructures, and accordingly we need to create a nanoscale source, drain and
gate. One feasible nanostructure to
build such a transistor from is the quantum dot.
A quantum dot is “a semiconductor nanostructure that
confines the motion of conduction band electrons, valence band holes, or
excitons (pairs of conduction band electrons and valence band holes) in all
three spatial directions. The confinement can be due to electrostatic
potentials (generated by external electrodes, doping, strain, impurities), due
to the presence of an interface between different semiconductor materials (e.g.
in the case of self-assembled quantum dots), due to the presence of the
semiconductor surface (e.g. in the case of a semiconductor nanocrystal), or due
to a combination of these. A quantum dot has a discrete quantized energy
spectrum. The corresponding wave functions are spatially localized within the
quantum dot, but extend over many periods of the crystal lattice. A quantum dot
contains a small finite number (of the order of 1-100) of conduction band
electrons, valence band holes, or exciton, i.e. a finite number of elementary
electric charges.” http://en.wikipedia.org/wiki/Quantum_dot.
Essentially, quantum dots are small regions defined in
a semiconductor material for those who are not well versed in Solid State
Physics. For those who are quantum dots
are used for studying the physics of artificial atoms, coupled quantum systems,
quantum chaos, the quantum Hall effect, and time-dependent quantum mechanics as
well. “In recent electron transport
experiments it has been shown that the same physics also occurs in molecular systems
and in small metallic grains.” http://marcuslab.harvard.edu/papers/KouwenhovenReview.pdf
Quantum dots are used
in medical research applications, photovoltaic cells, diode
lasers, amplifiers, and biological sensors due to superior transport and
optical properties. Again, for those who
know Solid State Physics this is because quantum dots are quasi-zero
dimensional structures with a sharp density of states relative to higher dimensional
structures.
Image: http://marcuslab.harvard.edu/papers/KouwenhovenReview.pdf
The image above shows two
constructions of the transistor using a quantum dot. According to http://www.estd.nrl.navy.mil/6870/6870.html,
many new nanoscale devices have been proposed, such as those based on
interference phenomena, conductance quantization, and Coulomb blockade effects
because most of
“the effort in nanoelectronics research has been directed at studying electron
transport in laterally-defined nanometer-scale structures in the hopes that
phenomena might be discovered that could form the basis for novel electronic
devices.” Yet, a problem with lateral device
features is that “they are too large for either the quantized confinement
energy or the capacitive charging energy to dominate kT at practical operating
temperatures, thus rendering them unfeasible for all but a few specialized
applications.” Therefore, as shown in
the above image, for most realizable applications, the vertical geometry might
be the way to go.
Self Assembly of Nanostructures
Another important concept is that of Self
Assembly. Since nanostructures are small
and many, it is inefficient to have to individually connect each piece for
large scale production of the nanostructures.
Chemical Self Assembly
Physical Self Assembly
Colloidal Self Assembly
Hybrid Si-biological Systems
Cellular Automata
DNA Computing
Quantum Electronics or Spintronics
Quantum Computing
System Defects, Redundancy and Probabilities
(Reliability Issue)
In the processes discussed, defects,
uncertainties and probabilities are unavoidable. It is through redundancy we attempt to solve
our problems in these matters. This
solution is based upon the model presented to us by nature itself. For example, in every life form of Earth,
from bacteria to human being, there exist DNA–and in order to preserve the
integrity and precision of the system, the same DNA sequences are found to be
repeated in an organism cell(s). Another
example is human communication. Often,
people repeat their ideas multiple times and in multiple ways not only for emphasis
but also to ensure the integrity and precision of the communication. The idea behind redundancy is “error
prevention.”
Because these systems are small and
cheap, but less reliable, it becomes crucial that the calculations are repeated
thousands of times so that the laws of probability and statistics can be used
to ensure the integrity and precision of the calculations whether they are
logical or arithmetic. This probability
theme therefore applies to everything from the Crossbar Architecture to DNA
Computing to Quantum Computing or Spintronics.
In the case of the Crossbar Architecture if the switches fail in the “open” state,
then many more defects can be tolerated than if they fail in the “closed”
state. Failure in the closed state will
leave the entire row or column of associated gates
inoperable. In the case of human DNA how
much redundancy is present for a certain gene is also a reflection of how
crucial that gene is to the organism.
Power Dissipation Issue
http://www.cs.caltech.edu/cbsss/finalreport/nanoscale_ind_figueiredo.pdf
The Labs and Companies:
Related Keywords:
Spintronics, CMOS, Nanoelectronics
Books, Journals and References:
Mittal, Wong, Cao, and Starr. Nano-CMOS
Circuit and Physical Design. Wiley, 2003.
Bird, Jonathan
P. Electron Transport in Quantum Dots. Springer, 2003.
Zhirnov and Herr. “New Frontiers:
Self-Assembly and Nanoelectronics.” Computer
(January 2001): 34-43. Available at http://csdl2.computer.org/dl/mags/co/2001/01/r1034.pdf
J. Heath, P.
Kuekes, G. Snider, S. Williams, A Defect-Tolerant Computer Architecture:
Opportunities for Nanotechnology, Science, Vol. 280, 12 June 1998, pp.
1716-1721.
http://pavel.physics.sunysb.edu/~likharev/nano/IEEENANO05.pdf
- Afterlife for Silicon: CMOL Circuit Architectures by Xialong
Ma, Dmitri B. Strukov, Jung Hoon Lee, and Konstantin K. Likharev* of
http://www.iaik.tugraz.at/teaching/05_vlsi-design/slides/10_nanotechnology.pdf
- a slide show summarizing the effects of shrinking CMOS technology
http://www.csee.umbc.edu/~plusquel/vlsi/slides/c1_tech.html
- succinct webpage giving comparison of IC technologies
http://news.com.com/Spintronics+may+save+Moores+Law/2100-1008_3-6048228.html?tag=st.ref.goo
– Spintronics
http://news.com.com/Moore+says+nanoelectronics+face+tough+challenges/2100-1006_3-5607422.html
- Intel’s Cofounder Gordon Moore talks
http://www.physics.mcgill.ca/~peter/nanoelectronics.htm
- a good summary of nanoelectronics, defines nanoelectronics from
microelectronics in favor of spintronics over silicon transistors
http://www.physics.mcgill.ca/~peter/
- physics Professor Peter Grütter’s work in nanoelectronics
http://www.imec.be/wwwinter/mediacenter/en/SR2005/html/142187.html
- Post-CMOS
nanotechnology IIAP from Imec
http://rsfq1.physics.sunysb.edu/~likharev/nano/NanoGiga031603.pdf
- A nice detailed paper on “Electronics below 10 nm”
http://domino.research.ibm.com/comm/pr.nsf/pages/news.20010425_Carbon_Nanotubes.html
- Chip Evolution: IBM Scientists Develop Breakthrough Transistor Technology
with Carbon Nanotubes
http://www.estd.nrl.navy.mil/code6870/nanodev/nanodev.html
- nanoelectronic devices
http://spot.colorado.edu/~yangr/research.html
- Professor Ronggui Yang’s work in electron transport – requires a knowledge of solid state physics
http://www.nano.org.uk/news/newsarchive.htm
- recent nanotechnology news
http://www.trnmag.com/Stories/2004/090804/Chip_architecture_uses_nanowires_090804.html
- TRN Magazine article, “Chip Architecture Uses Nanowires.”
http://www.cs.caltech.edu/cbsss/finalreport/nanoscale_ind_figueiredo.pdf
-Reducing Power Dissipation in the Sublithographic Crossbar Architecture –
Paper by Robert Figueiredo of MIT
http://www.ecommercetimes.com/story/55194.html
- Jan 16, 2007, HP Researchers Give Chips a Nano Spin By Walaika
Haskins
http://scientificchess.com/articles/Nanotechnology.htm
- Nanotechnology by Aditya Mittal
http://marcuslab.harvard.edu/papers/KouwenhovenReview.pdf
- Electron Transport in Quantum Dots by Leo P. Kouwenhoven, Charles M. Marcus, Paul
L. Mceuen, Seigo Tarucha, Robert M. Westervelt, and Ned S. Wingreen.
http://www.research.ibm.com/nanoscience/nanotubes.html
- Nanotubes Research at IBM
http://www.estd.nrl.navy.mil/6870/6870.html
- Electronic Materials Branch – U.S. Navy Research Nanotechnology and Physics
of Semiconductors
Further
Electron Transport in Quantum Dots is a timely review covering topics such
as the Kondo effect and spin-dependent transport in tunnel coupled dots,
quantum chaos in open quantum dots and antidot arrays, and explorations of the
novel technological applications of quantum dots and carbon nanotubes. It is
unique in that it:
- Brings together contributions from some of the most widely-recognized experts
in this important field of research;
-Provides the most comprehensive, yet wide-ranging, review of this important
field to date;
- Features a self-contained format that should make it a useful text for
introductory graduate studies of this important field. This book will be of
interest to researchers, university faculty, and graduate students in physics
and electrical engineering, particularly those who are engaged in research into
the fundamental properties, and technological applications, of nanostructures
and nanoelectronic devices.
Electron Transport in Quantum Dots is
written for:
Researchers, university faculty,
graduate students in physics and electrical engineering, particularly those who
are engaged in research into the fundamental properties, and technological
applications, of nanostructures and nanoelectronic devices